Lower power consumption has been gaining importance in microprocessor and microcontroller design due to wide spread use of portable and handheld applications. A typical embedded control system will generally include a central processing unit (CPU) and a variety of different types of memory and peripheral devices. The different types of memory may be external to an integrated circuit having the microcontroller, and/or on the same integrated circuit, and may include cache memory, ROM (read only memory), and a variety of SRAM (static random access memory) devices.
A significant amount of energy and time is required to access a large external main memory. Therefore, a smaller, faster, and more efficient memory, sometimes referred to as a cache, may be used on the integrated circuit to reduce the number of accesses to the main memory. To keep the size of the integrated circuit as small as possible, only as much memory as is necessary is included onboard the integrated circuit.
A cache TAG is frequently used to increase the performance of the cache. The cache TAG receives a TAG address that is provided by the microprocessor and determines if the requested instructions and/or data are present in the cache memory. If a requested instruction is not located in the cache, the microprocessor must then retrieve the instruction from the main memory. When an instruction is written into the cache, the higher order bits of the address of the instruction are stored in a TAG array. The cache TAG also has a comparator that compares a processor generated address to the TAG address. If the TAG address and the processor generated address are the same, a cache "hit" occurs, and a match signal is provided by the cache TAG, indicating that the requested data is located in the cache memory. If the processor generated address and the TAG address are not the same, a cache "miss" occurs, and the match signal indicates that the requested data is not located in the cache memory. In addition, a valid bit may be set as a part of the TAG address for qualifying a valid hit of the stored TAG address during a compare cycle of the cache.
There may be several levels of hierarchy in the memory system of a high performance microprocessor in order to boost efficiency of instruction and data retrieval. Power consumed by the CPU to retrieve instructions and data is typically much higher when the instructions and data are fetched from another level in the memory system. Therefore, reducing the number of instruction fetches to another level of memory is desirable to reduce power consumption, especially in applications that are battery powered.
Also, some applications often spend a significant portion of their execution time on small program loops. An example of such an application would be an implementation of a filter for digital signal processing. Having to repeatedly access a main memory for all, or a part, of these instructions would have an adverse effect upon both power consumption and execution speed. Therefore, it would be desirable to reduce power consumption and increase execution speed associated with the execution of such small loops by avoiding the need to repeatedly access main memory, while at the same time, reducing the surface area required to implement the cache.